Generally, semiconductor materials (e.g., silicon) used in fabrication of integrated circuit (IC) devices are implanted with different dopants/ions (e.g., charge carries) in order to change the conductivity of the semiconductor material. The ion implantation may be performed during front-end-of-line (FEOL) processes or later during back-end-of-line (BEOL) processes. In one instance, when forming a transistor, corresponding areas for its source and drain regions in a polysilicon substrate may be implanted with an n-type or a p-type dopant to form an n-type or a p-type transistor, respectively. Usually, the implanting process utilizes an implantation beam pulse to accelerate and guide the ions to the target area on the substrate. However, with advances in IC design and fabrication technologies, IC area is reduced for improved active/idle power consumption, which introduces new challenges for the ion implantation processes. For example, ICs utilizing FINFET (e.g., tri-gate) devices require different considerations for implanting dopants on surfaces of the FINFET fins.
FIGS. 1A and 1B schematically illustrate transistors in example ICs. Adverting to FIG. 1A, diagram 100 is of a conventional planar metal-oxide-semiconductor field-effect-transistor (MOSFET), which includes a silicon substrate 101, an oxide layer 103, a source region 105, a drain region 107, and a logic gate 109. For a planar device such as in FIG. 1A, an ion implantation process may utilize an implantation beam pulse 111 that is substantially perpendicular to the source and drain region surfaces on the substrate 101.
FIG. 1B illustrates an example IC device 150 that includes a plurality of FINFET type transistors 113, 115, and 117, with a common logic gate 119, wherein each transistor includes corresponding source and drain structures, 113a and 113b, 115a and 115b, and 117a and 117b, which are formed around vertical FINFET fins on the substrate 101. The logic gate 119 wraps around the top and sidewall surfaces of each fin structure for controlling a current flow from the source to the drain region of the fin. Similar to the IC device in the example 100, the source and drain regions need to be implanted with dopants in order to facilitate the current drain from the source portion of the fin to the drain portion of the fin. However, a substantially vertical implantation beam pulse, such as pulse 111, may not be able to properly implant sidewall surfaces of the fins, nor can an angled or tilted beam, as limited spacing between adjacent fins may prevent (e.g., shadowing effects) implanting top and sidewall surfaces of each fin with uniform depths and concentration levels of dopants. For example, implanting beam pulse 111a may be utilized to implant top and sidewall surfaces of the drain 115b with dopants. However, the top surface of the drain 115b may be implanted with a higher concentration level when compared to its sidewall surfaces. Moreover, even if an angled/tilted implantation beam pulse 111b is utilized to implant a dopant onto the sidewall surfaces of the drain 115b, because of close proximity of drains 113b and 115b or the drains 115b and 117b, the sidewall surfaces of the drain 115b may not be uniformally or sufficiently implanted with the dopant. For performance and margin at a FINFET device, it is essential to minimize differences in implanting dopants on top and sidewall surfaces of the FINFET fins.
A need therefore exists for a methodology to implant dopants onto FINFET fin surfaces with uniform concentration and depth levels of the dopants and the resulting device.